Accommodating workload diversity in chip multiprocessors

Slipstream Processors: Improving both Performance and Fault Tolerance. Patt, (ASPLOS 2010) MT on CMPs Jose Renau† Karin Strauss Luis Ceze Wei Liu Smruti Sarangi James Tuck Josep Torrellas; Energy-Efficient Thread-Level Speculation on a CMP S.

Proceedings of the 9th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), pp. [pdf] EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system Pdf Perry H. Yang, Guei-Yuan Lueh , Hong Wang Accurate Branch Prediction for Short Threads, Bum Yong Choi, Leo Porter, Dean M.

Slipstream Processors: Improving both Performance and Fault Tolerance. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Proceedings of the 9th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), pp. [pdf] Necromancer: Enhancing System Throughput by Animating Dead Cores ( pdf ) Amin Ansari, Shuguang Feng, Shantanu Gupta, and Scott Mahlke Proc.

As the available concurrency varies widely for diverse applications or different execution phases of an individual program, the number of resource allocated should be adjusted dynamically for high utilization rate while not compromising performance.

In this paper, aiming at resource management in flexible architecture, an implementation of confidence predictor, referred as speculative depth estimator (SDE), is introduced, which is able to conduct the real-time resource tuning.

Abstract Nowadays, most chip multiprocessor (CMP) designs face the challenge of how to keep the balance between on-chip parallelism, communication overhead, program performance, and resource utilization.

By using the conception of physical core and logical processor, flexible-core CMPs(FCMPs) provide more optimization space.

in 20th International Symposium on Computer Architecture, May 1993.

Transactional memory: Architectural support for lock-free data structures,.

Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semiconductor industry.

Using worst case latency/power assumptions is one option to address process variations.

While these schemes operate with profile data, they can be made to work with partial profiling as well with the help of curve fitting.